This invention relates to programmable logic devices (PLDs), and, more particularly, to specialized processing blocks which may be included in such devices.
As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, a PLD sold by Altera Corporation, of San Jose, Calif., under the name STRATIX® II includes DSP blocks, each of which includes four 18-by-18 multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-by-18 multipliers, but also as four smaller multipliers, or as one larger (36-by-36) multiplier. In addition, one 18-by-18 complex multiplication (which decomposes into two 18-by-18 multiplication operations for each of the real and imaginary parts) can be performed.
Such a DSP block may be configured as a finite impulse response (FIR) filter, with 18-bit data and coefficients. Each block may be used to perform the summation of four 18-by-18 multiplications to form a 4-tap sub-block of a longer FIR filter.
Many types of FIR filters may be encountered. Two of those types are an interpolation FIR filter—in which the number of samples is increased by a factor of n by inserting (“interpolating”) n−1 samples between adjacent samples—and a decimation FIR filter—in which the number of samples is decreased by a factor of n by removing n−1 out of every n samples. A DSP block that may be configured as different types of filters, including an interpolation FIR filter and a decimation FIR filter, is shown in copending, commonly-assigned U.S. patent application Ser. No. 11/447,370, filed Jun. 5, 2006, which is hereby incorporated by reference herein in its entirety.
One application of interpolation and decimation filters is in wireless communication systems based on TDD (time division duplexing) mode, such as GSM, 3G LTE and TD-CDMA. In those systems, a filter may need to work some of the time in decimation mode, and some of the time in interpolation mode. For example, such systems include digital up-converters (DUCs), which include interpolation filters, and digital down-converters (DDCs), which include decimation filters. Separate filters can be included for the DUCs and the DDCs, but the DUCs and the DDCs never operate at the same time, meaning that at any one time, half of the filters would be idle. Therefore, there would be efficiencies, in terms of the number of multipliers used, if a single filter could operate in either interpolation mode or decimation mode on demand, changing modes in real time “on the fly.” However, it has heretofore been difficult to create a filter which can be switched between the two modes during run time, and at the same time uses as few multipliers as possible.
It would be desirable to be able to provide, in a PLD, a specialized processing block, such as a DSP block, that can be configured as a FIR filter capable of performing both interpolation and decimation and of changing modes in real time.